The present invention is directed to integrated circuits. More particularly, the invention provides a system and method for electrostatic discharge protection. Merely by way of example, the invention has been applied to signals at various voltages. But it would be recognized that the invention has a much broader range of applicability.
For signals at various voltages, excessive electrostatic discharges (ESD) can cause failure of an integrated circuit. Therefore a robust on-chip ESD protection circuit is often required to protect the internal semiconductor circuitry. For example, the ESD protection circuit includes a triggering mechanism. When a pin voltage falls outside certain operating conditions, the triggering element enables the ESD protection circuit to conduct most of the ESD current. On the other hand, under normal operation conditions, the triggering mechanism should often ensure the ESD protection circuit remains in an off state.
FIG. 1 is a simplified conventional system for ESD protection. A system 100 includes an NMOS transistor 110, a capacitor 120, and a resistor 130. The NMOS transistor 110 is a large transistor and coupled to both pads 140 and 150. The capacitor 120 is connected to the pad 140, and the resistor 130 is connected to the pad 150. As shown in FIG. 1, the pad 140 provides a signal to an internal circuit, which is protected by the system 100. The pad 150 is biased to a ground voltage level of Vss. The capacitor 120 and the resistor 130 can provide a triggering mechanism. For example, the gate of the transistor 110 is grounded through the resistor 130 during normal operation. The NMOS transistor usually remains in an off state. During an ESD event, the voltage level at the pad 140 changes quickly with time. Therefore, the gate of the transistor 110 is AC-coupled through the capacitor 120 up to above the threshold voltage of the NMOS transistor 110. The NMOS transistor 110 is thus turned on to conduct the ESD current. The system 100 has certain weaknesses in high-voltage applications. For example, the NMOS transistor 110 can be turned on by high voltage transient signal at the pad 140 even during normal operation. The system 100 may thus interfere with the normal operation of the internal circuit.
Hence it is highly desirable to improve techniques for ESD protection.